Final Results
Creating the POWERALU using the VLSI design process taught us a lot. We created an 8 bit ALU capable of standard arithmatic operations as well as SRT division. The Verilog code, SignalScan simulations, Magic layouts, and IRsim results for the various components of the ALU can be seen through the links below.
ALU Main Module:
Final Report
Verilog Code
Initial Simulation [1] [1b] [2] [2b] [3]
Magic Layout [ALU] [in Pad]
Timing Simulation [1] [2] [3]
ALU components:
Bitwise module
SRT Division unit
41 by 8 bit Mux