ECE 429 PROJECT

ARCHITECTURE DESIGN

 

DESCRIPTION: The POWERALU can take 7 instructions (adding, subtracting, and-ing, or-ing, loading, dividing and not-ing). An 8th instruction will place the ALU in the do-nothing mode, where the contents of the Accumulator are preserved. The Op_type bits have been selected as to minimize the necessary logic.

Instruction

Op_type bits

Add A

000

Sub A

001

And A

010

Or A

011

Not A

111

Div A

101

Load A

110

do_nothing

100

It is easy to see that the first two MSB of the Op_type can be used as selector for the 41x8 mux that controls the input to the Accumulator. A 00 would select an arithmetic operation (and take the output from the Adder/Subtractor), a 01 would select a logic operation (and take the output from the AndOrNot block), a 10 would select the division operation (and take the output from the Radix-2 SRT Divider), and finally, a 11 would select loading. The only exception is for the Not operation. In this case, the MSB bit of the Op_type must be changed through logic (2 gates are sufficient) to a logic value of 0 before feeding it into the mux selector. See logic below:



Bit Op_type[0] can be used as the Cin input to the Adder/Subtractor. This selection was useful not only because the Add and Sub Instruction op-types differ by only one bit (namely the LSB, which is 1 for Sub and 0 for Add), but also because the LSB of the op-type for Division is also 1. This enables the ALU to perform concurrent Division and Subtraction operations. In this situation the Adder/Subtractor will act as a comparator. If the result of the subtraction is positive (MSB of the Adder/Subtractor output is 0), than it means the Divider is greater than the Divisor of the Division. This would assert the Error output signal of the ALU.

The SRT block is controlled by three signals Load, Reset and Start. As shown in the SRT simulation, the Start signal must be kept asserted while the Clock signal reaches a positive edge, and after that the Start signal must be deasserted. The Load signal must be kept high for the duration of the division computation, and turned low only after the negative clock edge after which the Quotient reached its correct value. In that moment, the Load signal must be deasserted prior to the following rising clock edge, so that the result is not further changed. It is important to mention that within the SRT block, the 9bit register that records the partial remainders and the on-the-fly conversion mechanism operate at different times. The first operates on positive Clock edges while the latter operates on negative edges.

r0 = X

   

0

.0

1

0

1

0

1

0

1

 

2r0

   

0

.1

0

1

0

1

0

1

0

>= 1/2 set q1 = 1

Add -D

+

 

1

.0

0

0

0

0

0

0

1

 


 

r1

   

1

.1

0

1

0

1

0

1

1

 

2r1

   

1

.0

1

0

1

0

1

1

0

< -1/2 set q2 = -1

Add D

+

 

0

.1

1

1

1

1

1

1

1

 


 

r2

   

0

.0

1

0

1

0

1

0

1

 

2r2

   

0

.1

0

1

0

1

0

1

0

>= 1/2 set q3 = 1

Add -D

+

 

1

.0

0

0

0

0

0

0

1

 


 

r3

   

1

.1

0

1

0

1

0

1

1

 

2r3

   

1

.0

1

0

1

0

1

1

0

< -1/2 set q4 = -1

Add D

+

 

0

.1

1

1

1

1

1

1

1

 


 

r4

   

0

.0

1

0

1

0

1

0

1

 

2r4

   

0

.1

0

1

0

1

0

1

0

>= 1/2 set q5 = 1

Add -D

+

 

1

.0

0

0

0

0

0

0

1

 


 

r5

   

1

.1

0

1

0

1

0

1

1

 

2r5

   

1

.0

1

0

1

0

1

1

0

< -1/2 set q6 = -1

Add D

+

 

0

.1

1

1

1

1

1

1

1

 


 

r6

   

0

.0

1

0

1

0

1

0

1

 

2r6

   

0

.1

0

1

0

1

0

1

0

>= 1/2 set q7 = 1

Add -D

+

 

1

.0

0

0

0

0

0

0

1

 


 

r7

   

1

.1

0

1

0

1

0

1

1

 

2r7

   

1

.0

1

0

1

0

1

1

0

< -1/2 set q8 = -1

Add D

+

 

0

.1

1

1

1

1

1

1

1

 


 

r8

   

0

.0

1

0

1

0

1

0

1

 

Q = 0.01010101 = 0.33203125

The FSM necessary to operate this sequence of signals is shown below. It has two inputs: Division and MasterReset. The first one starts the sequence, while the latter one resets the FSM to the idle state (S0). The arrows shown in the figure correspond to the Division input.

It is important to note that this FSM by itself will not be able to deassert the Load signal only after the negative edge of the Clock (the FSM operates on positive edge clock signals). Therefore, additional logic is needed to ensure this. The answer lies in a negative edge triggered D flip-flop. See the figure below:

When reaching state S9 and Afterneg gets asserted, cancell_load will get a logical value 1 only after the negative clock edge. Through the means of an inverter and an AND gate, the cancell_load will bring "down" the Load signal to a logical value 0.